arXiv:2409.01141cs.ARcs.LG2024-09中稿 · MICRO 2024被引 73

Duplex通过混合处理器协同优化大模型推理,提升吞吐量并降低内存压力。

Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching

  • 采用xPU与Logic-PIM混合架构,按算力密度动态分配计算任务
  • 支持分组查询注意力与专家模型的联合处理,吞吐量显著提升
  • 适合需要高并发推理的大规模语言模型部署场景

大型语言模型(LLMs)因其在多样上下文中生成高质量内容的能力而兴起。为应对其不断增长的计算资源需求,混合专家(MoE)架构应运而生,可在保持参数量庞大的同时减少计算开销。结合先进的连续批处理技术虽能提升吞吐量,但会引发MoE和注意力层频繁访问DRAM,成为性能瓶颈。我们观察到,传统计算设备在处理这些低算术强度(Op/B)的层时效率低下,其中MoE层的Op/B至少为1,注意力层在分组查询注意力(Grouped Query Attention)下为4–8。现有存内计算(PIM)架构仅针对极低Op/B(低于1)操作优化,无法有效处理此类任务。为此,我们提出Duplex:一种集成面向高Op/B的xPU与面向低Op/B的Logic-PIM的统一硬件系统,可根据各层的Op/B自动选择最优处理单元。进一步提出专家与注意力协同处理机制,以最大化xPU与Logic-PIM的利用率。实验表明,该设计可高效支撑大规模模型推理。

原文摘要 · Abstract (English)

Large language models (LLMs) have emerged due to their capability to generate high-quality content across diverse contexts. To reduce their explosively increasing demands for computing resources, a mixture of experts (MoE) has emerged. The MoE layer enables exploiting a huge number of parameters with less computation. Applying state-of-the-art continuous batching increases throughput; however, it leads to frequent DRAM access in the MoE and attention layers. We observe that conventional computing devices have limitations when processing the MoE and attention layers, which dominate the total execution time and exhibit low arithmetic intensity (Op/B). Processing MoE layers only with devices targeting low-Op/B such as processing-in-memory (PIM) architectures is challenging due to the fluctuating Op/B in the MoE layer caused by continuous batching. To address these challenges, we propose Duplex, which comprises xPU tailored for high-Op/B and Logic-PIM to effectively perform low-Op/B operation within a single device. Duplex selects the most suitable processor based on the Op/B of each layer within LLMs. As the Op/B of the MoE layer is at least 1 and that of the attention layer has a value of 4-8 for grouped query attention, prior PIM architectures are not efficient, which place processing units inside DRAM dies and only target extremely low-Op/B (under one) operations. Based on recent trends, Logic-PIM adds more through-silicon vias (TSVs) to enable high-bandwidth communication between the DRAM die and the logic die and place powerful processing units on the logic die, which is best suited for handling low-Op/B operations ranging from few to a few dozens. To maximally utilize the xPU and Logic-PIM, we propose expert and attention co-processing.

大模型推理混合专家存内计算硬件优化

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