用深度学习提升芯片设计中的超图划分效率
VLSI Hypergraph Partitioning with Deep Learning
- 构建模拟真实电路网表特征的合成基准数据集
- 提出具有已知最优切割质量上界的评估标准
- 验证图神经网络在实际芯片设计中的适用性
超图划分是计算机科学中的经典问题，在芯片设计流程中至关重要，其进展可显著影响设计质量和效率。深度学习技术，特别是图神经网络（GNN），在节点、边和图预测任务中表现出色，尤其在归纳与直推学习方法中。近年来，图池化层及其在图划分中的应用成为研究热点。尽管这些方法在社交网络、计算图等随机图中表现良好，但其在集成电路（VLSI）超图网表中的有效性尚未得到充分探索。本研究提出一组新的合成划分基准，模拟真实网表特征，并具备已知的最优切割质量上界。通过与现有最先进划分算法及基于GNN的方法对比，我们系统评估了各类方法的优势与局限。
原文摘要 · Abstract (English)
Partitioning is a known problem in computer science and is critical in chip design workflows, as advancements in this area can significantly influence design quality and efficiency. Deep Learning (DL) techniques, particularly those involving Graph Neural Networks (GNNs), have demonstrated strong performance in various node, edge, and graph prediction tasks using both inductive and transductive learning methods. A notable area of recent interest within GNNs are pooling layers and their application to graph partitioning. While these methods have yielded promising results across social, computational, and other random graphs, their effectiveness has not yet been explored in the context of VLSI hypergraph netlists. In this study, we introduce a new set of synthetic partitioning benchmarks that emulate real-world netlist characteristics and possess a known upper bound for solution cut quality. We distinguish these benchmarks with the prior work and evaluate existing state-of-the-art partitioning algorithms alongside GNN-based approaches, highlighting their respective advantages and disadvantages.
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