提出新型时域聚类均衡器，显著降低光通信系统能耗
Geometric Clustering for Hardware-Efficient Implementation of Chromatic Dispersion Compensation
- 基于时域抽头重叠机制设计聚类均衡算法
- 相比主流频域均衡器，能效提升70.7%，乘法器用量减少71.4%
- 适合追求低功耗的高速光通信硬件设计者
功耗效率仍是现代光纤通信系统的核心挑战，推动数字信号处理中计算复杂度的降低，尤其是色散补偿（CDC）算法。尽管已有多种复杂度降低策略，但多数缺乏硬件实现来验证其优势。本文针对相干接收机中的CDC滤波器抽头重叠效应进行理论分析，提出一种新型时域聚类均衡器（TDCE），并完成在FPGA上的硬件实现验证，支持长达640 km的光纤传输。通过与当前最先进的频域均衡器（FDE）在相同条件下的公平比较，发现并行化与内存管理等实现策略对硬件复杂度和能效的影响不亚于计算复杂度本身。所提出的TDCE硬件实现相较FDE，在计算复杂度更高情况下仍实现高达70.7%的能耗节省和71.4%的乘法器使用量减少。
原文摘要 · Abstract (English)
Power efficiency remains a significant challenge in modern optical fiber communication systems, driving efforts to reduce the computational complexity of digital signal processing, particularly in chromatic dispersion compensation (CDC) algorithms. While various strategies for complexity reduction have been proposed, many lack the necessary hardware implementation to validate their benefits. This paper provides a theoretical analysis of the tap overlapping effect in CDC filters for coherent receivers, introduces a novel Time-Domain Clustered Equalizer (TDCE) technique based on this concept, and presents a Field-Programmable Gate Array (FPGA) implementation for validation. We developed an innovative parallelization method for TDCE, implementing it in hardware for fiber lengths up to 640 km. A fair comparison with the state-of-the-art frequency domain equalizer (FDE) under identical conditions is also conducted. Our findings highlight that implementation strategies, including parallelization and memory management, are as crucial as computational complexity in determining hardware complexity and energy efficiency. The proposed TDCE hardware implementation achieves up to 70.7\% energy savings and 71.4\% multiplier usage savings compared to FDE, despite its higher computational complexity.
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