FSL-HDnn用低功耗芯片实现端到端少样本学习，能效达5.7 TOPS/W。
FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and Hyperdimensional Computing
- 用权值聚类与超维计算结合，无须梯度更新
- 特征提取能效5.7 TOPS/W，分类学习0.78 TOPS/W
- 适合边缘设备的实时少样本学习任务
本文提出FSL-HDnn，一种在40 nm CMOS工艺下实现端到端特征提取、分类与片上少样本学习（FSL）的低功耗加速器，采用无梯度学习技术。核心包含两个低功耗模块：权值聚类特征提取器和超维计算（HDC）。特征提取器利用先进的权值聚类与模式复用策略优化CNN特征提取；而HDC作为轻量级少样本分类器，通过超维向量显著提升训练准确率，优于传统基于距离的方法。双模块协同使学习过程无需复杂梯度计算，大幅提高能效与性能。具体而言，FSL-HDnn在特征提取阶段达到5.7 TOPS/W的前所未有的能效，分类与学习阶段为0.78 TOPS/W，分别较当前最先进的CNN和FSL处理器提升2.6倍和6.6倍。
原文摘要 · Abstract (English)
This paper introduces FSL-HDnn, an energy-efficient accelerator that implements the end-to-end pipeline of feature extraction, classification, and on-chip few-shot learning (FSL) through gradient-free learning techniques in a 40 nm CMOS process. At its core, FSL-HDnn integrates two low-power modules: Weight clustering feature extractor and Hyperdimensional Computing (HDC). Feature extractor utilizes advanced weight clustering and pattern reuse strategies for optimized CNN-based feature extraction. Meanwhile, HDC emerges as a novel approach for lightweight FSL classifier, employing hyperdimensional vectors to improve training accuracy significantly compared to traditional distance-based approaches. This dual-module synergy not only simplifies the learning process by eliminating the need for complex gradients but also dramatically enhances energy efficiency and performance. Specifically, FSL-HDnn achieves an Intensity unprecedented energy efficiency of 5.7 TOPS/W for feature 1 extraction and 0.78 TOPS/W for classification and learning Training Intensity phases, achieving improvements of 2.6X and 6.6X, respectively, Storage over current state-of-the-art CNN and FSL processors.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。