AIvril让AI生成的硬件代码更准更可靠，自动纠错验证
AIvril: AI-Driven RTL Generation With Verification In-The-Loop
- 多智能体系统自动修正语法错误并验证功能
- 代码质量提升近2倍，验证成功率88.46%
- 适合追求高可靠性AI硬件设计的工程师
大型语言模型（LLMs）具备处理复杂自然语言任务的能力，有望重塑整个硬件设计流程，未来可能实现前端与后端任务的全面自动化。目前，LLMs在加速寄存器传输级（RTL）生成方面展现出巨大潜力，显著提升效率与创新速度。然而，其概率性特征易导致生成错误，这在对精度和可靠性要求极高的RTL设计中构成重大挑战。为此，本文提出AIvril框架，采用多智能体、不依赖特定LLM的设计，实现自动语法修正与功能验证，显著减少甚至完全消除错误代码生成。在VerilogEval-Human数据集上的实验表明，该框架相较以往方法使代码质量提升近2倍，验证目标达成率达88.46%。这标志着向自动化、优化的硬件设计流程迈出关键一步，为基于AI的RTL设计提供更可靠的方案。
原文摘要 · Abstract (English)
Large Language Models (LLMs) are computational models capable of performing complex natural language processing tasks. Leveraging these capabilities, LLMs hold the potential to transform the entire hardware design stack, with predictions suggesting that front-end and back-end tasks could be fully automated in the near future. Currently, LLMs show great promise in streamlining Register Transfer Level (RTL) generation, enhancing efficiency, and accelerating innovation. However, their probabilistic nature makes them prone to inaccuracies - a significant drawback in RTL design, where reliability and precision are essential. To address these challenges, this paper introduces AIvril, an advanced framework designed to enhance the accuracy and reliability of RTL-aware LLMs. AIvril employs a multi-agent, LLM-agnostic system for automatic syntax correction and functional verification, significantly reducing - and in many cases, completely eliminating - instances of erroneous code generation. Experimental results conducted on the VerilogEval-Human dataset show that our framework improves code quality by nearly 2x when compared to previous works, while achieving an 88.46% success rate in meeting verification objectives. This represents a critical step toward automating and optimizing hardware design workflows, offering a more dependable methodology for AI-driven RTL design.
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