用FPGA加速表格数据预处理，速度比CPU快71倍，降低资源消耗。
Efficient Tabular Data Preprocessing of ML Pipelines
- 设计专用硬件加速器Piper，用FPGA实现表格数据预处理
- 在二进制输入下比数据中心GPU快20.3倍，比128核CPU快71.3倍
- 适合大规模推荐系统训练，可显著提升数据流水线效率
机器学习训练中的数据预处理管道（包括数据解码、清洗和转换）是关键环节，但计算量大，常成为瓶颈。随着CPU与GPU性能差距扩大，需大量CPU才能满足GPU的吞吐需求，导致资源与能耗上升。当涉及词汇表生成时，因不同核心和服务器间存在行级同步开销，性能扩展性差。为此，本文提出Piper——一种面向表格数据预处理的硬件加速器，基于FPGA原型验证。结果表明，在延迟上相比128核CPU服务器提速4.7至71.3倍；在使用二进制输入时，比数据中心GPU快4.8至20.3倍。该性能展示了其在商业推荐系统训练管道中提升效率、大幅降低资源消耗的巨大潜力。
原文摘要 · Abstract (English)
Data preprocessing pipelines, which includes data decoding, cleaning, and transforming, are a crucial component of Machine Learning (ML) training. Thy are computationally intensive and often become a major bottleneck, due to the increasing performance gap between the CPUs used for preprocessing and the GPUs used for model training. Recent studies show that a significant number of CPUs across several machines are required to achieve sufficient throughput to saturate the GPUs, leading to increased resource and energy consumption. When the pipeline involves vocabulary generation, the preprocessing performance scales poorly due to significant row-wise synchronization overhead between different CPU cores and servers. To address this limitation, in this paper we present the design of Piper, a hardware accelerator for tabular data preprocessing, prototype it on FPGAs, and demonstrate its potential for training pipelines of commercial recommender systems. Piper achieves 4.7 $\sim$ 71.3$\times$ speedup in latency over a 128-core CPU server and outperforms a data-center GPU by 4.8$\sim$ 20.3$\times$ when using binary input. The impressive performance showcases Piper's potential to increase the efficiency of data preprocessing pipelines and significantly reduce their resource consumption.
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