用大模型精准定位Verilog代码功能错误，效率远超传统方法。
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
- 基于大模型分析设计说明与错误代码，自动定位功能缺陷位置。
- 在RTLLM数据集上定位准确率达93.3%，优于GPT-4的77.9%。
- 无需测试平台或EDA工具，适合硬件开发者快速调试。
Verilog代码中的错误定位是硬件设计验证中关键且耗时的任务。尽管大型语言模型（LLMs）展现出强大的编程能力，但尚未有研究将其应用于Verilog代码的错误定位。本文提出Location-is-Key（LiK），一个开源的LLM解决方案，用于定位Verilog片段中的功能错误。在基于RTLLM的测试数据集上，LiK实现了93.3%的pass@1定位准确率，超过GPT-4的77.9%，接近Claude-3.5的90.8%。此外，LiK提供的错误定位显著提升了GPT-3.5的修复效率，功能修复通过率从40.39%提升至58.92%，凸显了定位精度在基于LLM的Verilog调试中的重要性。相比现有方法，LiK仅需设计说明和错误代码片段，无需测试平台、断言或任何EDA工具。该研究验证了使用LLM进行Verilog错误定位的可行性，为自动化Verilog代码调试提供了新方向。
原文摘要 · Abstract (English)
Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their strong programming capabilities. However, no work has yet considered using LLMs for bug localization in Verilog code. This paper presents Location-is-Key, an opensource LLM solution to locate functional errors in Verilog snippets. LiK achieves high localization accuracy, with a pass@1 localization accuracy of 93.3% on our test dataset based on RTLLM, surpassing GPT-4's 77.9% and comparable to Claude-3.5's 90.8%. Additionally, the bug location obtained by LiK significantly improves GPT-3.5's bug repair efficiency (Functional pass@1 increased from 40.39% to 58.92%), highlighting the importance of bug localization in LLM-based Verilog debugging. Compared to existing methods, LiK only requires the design specification and the erroneous code snippet, without the need for testbenches, assertions, or any other EDA tools. This research demonstrates the feasibility of using LLMs for Verilog error localization, thus providing a new direction for automatic Verilog code debugging.
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