构建首个硬件设计图表示学习基准，涵盖13项任务与5个数据集。
A Benchmark on Directed Graph Representation Learning in Hardware Designs
- 设计五大数据集与十三项预测任务，覆盖不同电路抽象层级。
- 双向消息传递网络与定向位置编码显著提升模型性能，最优模型跨任务超越基线。
- 强调分布外泛化能力不足，适合硬件与机器学习交叉研究者使用。
为应对现代计算系统设计复杂度的快速提升，有向图表示学习（DGRL）在编码电路网表、计算图及构建硬件性能预测代理模型方面变得至关重要。然而，由于缺乏全面且易用的基准，该领域在硬件方向仍相对未被充分探索。本研究提出一个新基准，包含五个硬件设计数据集和13项跨越不同电路抽象层次的预测任务。我们评估了21种DGRL模型，采用多种图神经网络与图变压器（GTs）作为主干，并结合针对有向图设计的位置编码（PE）。结果表明，双向（BI）消息传递神经网络（MPNN）与鲁棒的PE能显著提升性能。最先进模型包括结合了PE增强的GT与BI-MPNN层的混合架构，以及BI-图同构网络，在全部13项任务中均优于基线。此外，对分布外（OOD）性能的分析强调了当前DGRL模型在泛化能力上的迫切改进需求。该基准以模块化代码实现，便于硬件与机器学习研究者高效评估各类模型。
原文摘要 · Abstract (English)
To keep pace with the rapid advancements in design complexity within modern computing systems, directed graph representation learning (DGRL) has become crucial, particularly for encoding circuit netlists, computational graphs, and developing surrogate models for hardware performance prediction. However, DGRL remains relatively unexplored, especially in the hardware domain, mainly due to the lack of comprehensive and user-friendly benchmarks. This study presents a novel benchmark comprising five hardware design datasets and 13 prediction tasks spanning various levels of circuit abstraction. We evaluate 21 DGRL models, employing diverse graph neural networks and graph transformers (GTs) as backbones, enhanced by positional encodings (PEs) tailored for directed graphs. Our results highlight that bidirected (BI) message passing neural networks (MPNNs) and robust PEs significantly enhance model performance. Notably, the top-performing models include PE-enhanced GTs interleaved with BI-MPNN layers and BI-Graph Isomorphism Network, both surpassing baselines across the 13 tasks. Additionally, our investigation into out-of-distribution (OOD) performance emphasizes the urgent need to improve OOD generalization in DGRL models. This benchmark, implemented with a modular codebase, streamlines the evaluation of DGRL models for both hardware and ML practitioners
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