arXiv:2410.07364physics.opticscs.AI2024-10被引 2

用FPGA加速荧光寿命成像,实现多像素并行处理,提升实时性。

Unlocking Real-Time Fluorescence Lifetime Imaging: Multi-Pixel Parallelism for FPGA-Accelerated Processing

  • 在FPGA上部署GRU序列模型,结合压缩版轻量模型实现高效并行计算。
  • 通过任务调度优化,相比手动调度提速17.7倍(原模型)和52.0倍(轻量版)。
  • 适合需要低延迟荧光成像的临床手术导航与动态生物过程监测场景。

荧光寿命成像(FLI)是生物医学中用于测量荧光分子衰减时间的重要技术,可揭示代谢状态、蛋白质相互作用及配体-受体结合情况。然而,其在快速生物过程监测和临床手术引导中的应用受限于数据采集时间长、计算密集型后处理等问题。尽管深度学习已减少后处理耗时,但时间分辨数据采集仍是实时应用的瓶颈。为此,本文提出基于FPGA硬件加速的实时FLI方法。具体地,在兼容时间分辨相机的FPGA板上实现了基于门控循环单元(GRU)的序列到序列(Seq2Seq)模型。该模型在资源受限的FPGA(如有限的DSP单元和BRAM)下兼顾精度与效率。为应对存储与计算资源限制,采用STOMP——一种基于队列的离散事件仿真器,自动化优化任务调度与内存管理。通过集成原始的Seq2Seq模型及其经知识蒸馏压缩得到的轻量版本Seq2SeqLite,实现多像素并行处理,显著降低延迟。研究探索了不同层次的并行度,以平衡性能与资源利用。结果表明,所提方法在原始模型上相较手动调度实现17.7倍加速,在轻量模型上实现52.0倍加速。

原文摘要 · Abstract (English)

Fluorescence lifetime imaging (FLI) is a widely used technique in the biomedical field for measuring the decay times of fluorescent molecules, providing insights into metabolic states, protein interactions, and ligand-receptor bindings. However, its broader application in fast biological processes, such as dynamic activity monitoring, and clinical use, such as in guided surgery, is limited by long data acquisition times and computationally demanding data processing. While deep learning has reduced post-processing times, time-resolved data acquisition remains a bottleneck for real-time applications. To address this, we propose a method to achieve real-time FLI using an FPGA-based hardware accelerator. Specifically, we implemented a GRU-based sequence-to-sequence (Seq2Seq) model on an FPGA board compatible with time-resolved cameras. The GRU model balances accurate processing with the resource constraints of FPGAs, which have limited DSP units and BRAM. The limited memory and computational resources on the FPGA require efficient scheduling of operations and memory allocation to deploy deep learning models for low-latency applications. We address these challenges by using STOMP, a queue-based discrete-event simulator that automates and optimizes task scheduling and memory management on hardware. By integrating a GRU-based Seq2Seq model and its compressed version, called Seq2SeqLite, generated through knowledge distillation, we were able to process multiple pixels in parallel, reducing latency compared to sequential processing. We explore various levels of parallelism to achieve an optimal balance between performance and resource utilization. Our results indicate that the proposed techniques achieved a 17.7x and 52.0x speedup over manual scheduling for the Seq2Seq model and the Seq2SeqLite model, respectively.

荧光成像FPGA加速实时处理深度学习

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