用3nm工艺的多端口SRAM实现高效脉冲神经网络推理与在线学习。
Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning
- 设计多端口SRAM，支持并行读写与动态调度，提升计算吞吐。
- 在3nm FinFET上实现44MInf/s吞吐，每比特能耗607pJ，能效提升2.2倍。
- 适用于边缘设备，特别适合电池供电的智能传感系统。
当前人工智能计算系统面临内存墙问题，制约整体性能，尤其在智能手机、可穿戴设备和物联网传感器等电池受限的边缘设备中。本文提出一种面向脉冲神经网络（SNN）推理的基于SRAM的存内计算（CIM）加速器。所提架构采用多端口SRAM设计，包含多个独立读端口以提升吞吐量，并支持可重构读写端口以实现在线学习。此外，设计了仲裁电路，高效管理计算过程中的数据处理与端口分配。在3nm FinFET工艺下，128×128阵列实验显示，相比传统单端口设计，速度提升3.1倍，能效提高2.2倍。系统级实现达到44MInf/s吞吐，每推理消耗607pJ，功耗29mW。
原文摘要 · Abstract (English)
Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference. Our proposed architecture employs a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable Read-Write ports to facilitate online learning. Furthermore, we develop an Arbiter circuit for efficient data-processing and port allocations during the computation. Results for a 128$\times$128 array in 3nm FinFET technology demonstrate a 3.1$\times$ improvement in speed and a 2.2$\times$ enhancement in energy efficiency with our proposed multiport SRAM design compared to the traditional single-port design. At system-level, a throughput of 44 MInf/s at 607 pJ/Inf and 29mW is achieved.
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