22纳米芯片实现高能效循环神经网络加速，用于宽带功放数字预失真。
DPD-NeuralEngine: A 22-nm 6.6-TOPS/W/mm$^2$ Recurrent Neural Network Accelerator for Wideband Power Amplifier Digital Pre-Distortion
- 采用门控循环单元设计，软硬件协同优化提升效率。
- 每秒处理256.5亿次操作，能效达1.32 TOPS/W，ACPR达-45.3 dBc。
- 首款基于AI的功放预失真专用芯片，适合通信系统低功耗部署。
深度神经网络（DNN）在现代通信系统中用于数字预失真（DPD）的需求日益增长，亟需高效硬件实现。本文提出 DPD-NeuralEngine，一种基于门控循环单元（GRU）神经网络的超高速、小面积、低功耗专用加速器。通过软硬件协同设计，该22纳米CMOS芯片在2 GHz频率下运行，可处理最高250 MSps的I/Q信号。实验结果表明，其吞吐量达256.5 GOPS，功耗效率为1.32 TOPS/W，DPD线性化性能达到相邻信道功率比（ACPR）-45.3 dBc，误差矢量幅度（EVM）-39.8 dB。据我们所知，这是首个基于AI的功放数字预失真专用集成电路（ASIC），实现了6.6 TOPS/W/mm²的功耗-面积效率。
原文摘要 · Abstract (English)
The increasing adoption of Deep Neural Network (DNN)-based Digital Pre-distortion (DPD) in modern communication systems necessitates efficient hardware implementations. This paper presents DPD-NeuralEngine, an ultra-fast, tiny-area, and power-efficient DPD accelerator based on a Gated Recurrent Unit (GRU) neural network (NN). Leveraging a co-designed software and hardware approach, our 22 nm CMOS implementation operates at 2 GHz, capable of processing I/Q signals up to 250 MSps. Experimental results demonstrate a throughput of 256.5 GOPS and power efficiency of 1.32 TOPS/W with DPD linearization performance measured in Adjacent Channel Power Ratio (ACPR) of -45.3 dBc and Error Vector Magnitude (EVM) of -39.8 dB. To our knowledge, this work represents the first AI-based DPD application-specific integrated circuit (ASIC) accelerator, achieving a power-area efficiency (PAE) of 6.6 TOPS/W/mm$^2$.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。