通过软件级错误检测实现低功耗神经网络加速，节能超18%且无精度损失。
Shavette: Low Power Neural Network Acceleration via Algorithm-level Error Detection and Undervolting
- 利用算法级错误检测，无需硬件修改即可实现低电压运行。
- 在GPU上测试显示，能效提升18%~25%，精度不变，吞吐损失小于3.9%。
- 适用于现成设备，部署简单，适合嵌入式和移动端低功耗场景。
降低电压是提升数字电路能效的有效方法。本文提出一种仅通过软件修改即可实现深度神经网络（DNN）加速器低电压运行的简易方案。传统方法如时序错误检测（TED）系统开发成本高、开销大，且不适用于现成组件。本文方案基于算法级错误检测，开发成本低，无需电路改动，甚至可应用于通用设备。通过在主流DNN模型LeNet和VGG16上于GPU平台进行实验验证，结果表明：集成错误检测机制后，能效提升18%至25%，模型精度无损失，吞吐量下降不足3.9%。与需大量电路级修改或工具支持的TED方案相比，本方案设计集成更简便。
原文摘要 · Abstract (English)
Reduced voltage operation is an effective technique for substantial energy efficiency improvement in digital circuits. This brief introduces a simple approach for enabling reduced voltage operation of Deep Neural Network (DNN) accelerators by mere software modifications. Conventional approaches for enabling reduced voltage operation e.g., Timing Error Detection (TED) systems, incur significant development costs and overheads, while not being applicable to the off-the-shelf components. Contrary to those, the solution proposed in this paper relies on algorithm-based error detection, and hence, is implemented with low development costs, does not require any circuit modifications, and is even applicable to commodity devices. By showcasing the solution through experimenting on popular DNNs, i.e., LeNet and VGG16, on a GPU platform, we demonstrate 18% to 25% energy saving with no accuracy loss of the models and negligible throughput compromise (< 3.9%), considering the overheads from integration of the error detection schemes into the DNN. The integration of presented algorithmic solution into the design is simpler when compared conventional TED based techniques that require extensive circuit-level modifications, cell library characterizations or special support from the design tools.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。