超低功耗芯片实现高精度心律失常检测，适合植入设备
A 10.60 $μ$W 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection
- 采用混合位宽稀疏架构，1D CNN达50%稀疏度
- 实测仅10.60μW功耗，150 GOPS算力，准确率99.95%
- 功耗密度比顶尖方案低14.23倍，适配可穿戴医疗设备
本文提出一种超低功耗混合位宽稀疏卷积神经网络（CNN）加速器，用于加速室性心律失常（VA）检测。该芯片在量化后的1维CNN中实现了50%的稀疏度，采用稀疏处理单元（SPE）架构。在基于TSMC 40nm CMOS低功耗（LP）工艺的原型芯片上，针对VA分类任务的实测结果表明，其功耗仅为10.60 μW，算力达150 GOPS，诊断准确率达99.95%。计算能效密度仅为0.57 μW/mm²，较现有最先进工作降低14.23倍，极适合应用于可植入及可穿戴医疗设备。
原文摘要 · Abstract (English)
This paper proposes an ultra-low power, mixed-bit-width sparse convolutional neural network (CNN) accelerator to accelerate ventricular arrhythmia (VA) detection. The chip achieves 50% sparsity in a quantized 1D CNN using a sparse processing element (SPE) architecture. Measurement on the prototype chip TSMC 40nm CMOS low-power (LP) process for the VA classification task demonstrates that it consumes 10.60 $μ$W of power while achieving a performance of 150 GOPS and a diagnostic accuracy of 99.95%. The computation power density is only 0.57 $μ$W/mm$^2$, which is 14.23X smaller than state-of-the-art works, making it highly suitable for implantable and wearable medical devices.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。