用LLM+图神经网络，快速评估硬件代码质量
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
- 用图神经网络提取电路结构特征，增强LLM对硬件代码的理解
- 在OpenABCD数据集上优于现有基于图的RTL估计方法
- 可实时反馈代码质量，适合芯片设计迭代优化
逻辑综合是电路设计中的关键阶段，负责将硬件描述语言（HDL）设计转换为优化的网表。然而，传统逻辑综合方法计算成本高，限制了其在芯片设计迭代中的使用。近期大型语言模型（LLMs）在编程语言微调方面取得进展，提供了替代方案。本文提出通过训练预测网络，使LLM能够直接从HDL代码中估计电路质量，并利用在查找表（LUT）图上训练的图神经网络（GNN）嵌入进行正则化，从而融入底层电路知识。该方法在基准数据集OpenABCD上表现优于现有基于图的RTL级估计技术，且能提供对HDL代码质量的即时反馈。
原文摘要 · Abstract (English)
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditional logic synthesis methods are computationally intensive, restricting their iterative use in refining chip designs. Recent advancements in large language models (LLMs), particularly those fine-tuned on programming languages, present a promising alternative. This work proposes augmenting LLMs with predictor networks trained to estimate circuit quality directly from HDL code. To enhance performance, the model is regularized using embeddings from graph neural networks (GNNs) trained on Look-Up Table (LUT) graphs, thereby incorporating lower-level circuit insights. The proposed method demonstrates superior performance compared to existing graph-based RTL-level estimation techniques on the established benchmark OpenABCD, while providing instant feedback on HDL code quality.
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