用大模型分析Verilog代码的面积、延迟和功耗，提升硬件设计效率
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
- 构建包含2.5万份Verilog设计的基准数据集，支持推理任务
- 微调后模型在面积、延迟等指标上准确率提升超25%
- 比传统方法快1.7倍且无需预处理，适合芯片设计工程师
大型语言模型（LLMs）已被用于硬件设计中的多项任务，包括Verilog代码生成、EDA工具脚本编写和RTL错误修复。然而，目前尚未应用于后综合阶段的度量分析与估计。本文评估了LLMs对Verilog设计后综合指标的推理能力。提出MetRex，一个大规模数据集，包含25,868个Verilog HDL设计及其对应的面积、延迟和静态功耗数据，并引入链式思维（CoT）模板以增强推理能力。大量实验表明，监督微调（SFT）使模型在面积、延迟和静态功耗上的平均性能分别提升37.0%、25.3%和25.7%。尽管如此，复杂问题仍存在较大差距。相比现有最优回归模型，该方法在5%误差范围内预测成功的设计比例高出17.4%，且因无需预处理，实现1.7倍加速。本工作为推进基于LLM的Verilog度量推理奠定了基础。
原文摘要 · Abstract (English)
Large Language Models (LLMs) have been applied to various hardware design tasks, including Verilog code generation, EDA tool scripting, and RTL bug fixing. Despite this extensive exploration, LLMs are yet to be used for the task of post-synthesis metric reasoning and estimation of HDL designs. In this paper, we assess the ability of LLMs to reason about post-synthesis metrics of Verilog designs. We introduce MetRex, a large-scale dataset comprising 25,868 Verilog HDL designs and their corresponding post-synthesis metrics, namely area, delay, and static power. MetRex incorporates a Chain of Thought (CoT) template to enhance LLMs' reasoning about these metrics. Extensive experiments show that Supervised Fine-Tuning (SFT) boosts the LLM's reasoning capabilities on average by 37.0\%, 25.3\%, and 25.7\% on the area, delay, and static power, respectively. While SFT improves performance on our benchmark, it remains far from achieving optimal results, especially on complex problems. Comparing to state-of-the-art regression models, our approach delivers accurate post-synthesis predictions for 17.4\% more designs (within a 5\% error margin), in addition to offering a 1.7x speedup by eliminating the need for pre-processing. This work lays the groundwork for advancing LLM-based Verilog code metric reasoning.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。