优化图卷积硬件实现，提升事件视觉模型在FPGA上的扩展性。
Increasing the scalability of graph convolution for FPGA-implemented event-based vision
- 提出两步卷积法，用BRAM缓冲减少94%的LUT使用
- 在相同FPGA资源下支持更大图结构和更多网络层
- 适合需低功耗、高动态范围的移动机器人视觉系统
事件相机因其高时间分辨率、高动态范围、低功耗及事件数据稀疏性，正成为移动机器人中传统帧基视觉传感器的替代方案。充分发挥其优势需要高效算法与专用硬件平台。本文聚焦于异构SoC FPGA上图卷积神经网络（GCNN）的硬件模块优化，提出一种「两步卷积」方法，利用额外的BlockRAM缓冲，将乘法操作所需的LUT使用量最多降低94%。该方法显著提升了GCNN在FPGA上的可扩展性，使具有更多层数、更大图规模的模型得以部署，并适用于更动态的场景。
原文摘要 · Abstract (English)
Event cameras are becoming increasingly popular as an alternative to traditional frame-based vision sensors, especially in mobile robotics. Taking full advantage of their high temporal resolution, high dynamic range, low power consumption and sparsity of event data, which only reflects changes in the observed scene, requires both an efficient algorithm and a specialised hardware platform. A recent trend involves using Graph Convolutional Neural Networks (GCNNs) implemented on a heterogeneous SoC FPGA. In this paper we focus on optimising hardware modules for graph convolution to allow flexible selection of the FPGA resource (BlockRAM, DSP and LUT) for their implementation. We propose a ''two-step convolution'' approach that utilises additional BRAM buffers in order to reduce up to 94% of LUT usage for multiplications. This method significantly improves the scalability of GCNNs, enabling the deployment of models with more layers, larger graphs sizes and their application for more dynamic scenarios.
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