用查找表替代乘法器，让FPGA神经网络加速器跑得更快
LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference
- 用可重构的查找表实现高效乘法，突破传统乘法器限制
- 在ImageNet上达到1627张/秒推理速度，准确率70.95%
- 适合追求极致性能的FPGA部署场景
针对基于FPGA的神经网络加速器，传统上依赖数字信号处理（DSP）块完成乘法运算。本文提出LUTMUL，利用查找表（LUT）实现乘法操作。由于LUT数量通常比DSP多出约100倍，该方法展现出显著的计算优势。通过结合可重构数据流架构，本设计突破了传统基于DSP的峰值性能瓶颈，在FPGA上实现了更高效率的神经网络推理。实验表明，该方案在所有已知FPGA加速器中推理速度最快，ImageNet数据集上达到1627张/秒的吞吐量，同时保持70.95%的Top-1准确率。
原文摘要 · Abstract (English)
For FPGA-based neural network accelerators, digital signal processing (DSP) blocks have traditionally been the cornerstone for handling multiplications. This paper introduces LUTMUL, which harnesses the potential of look-up tables (LUTs) for performing multiplications. The availability of LUTs typically outnumbers that of DSPs by a factor of 100, offering a significant computational advantage. By exploiting this advantage of LUTs, our method demonstrates a potential boost in the performance of FPGA-based neural network accelerators with a reconfigurable dataflow architecture. Our approach challenges the conventional peak performance on DSP-based accelerators and sets a new benchmark for efficient neural network inference on FPGAs. Experimental results demonstrate that our design achieves the best inference speed among all FPGA-based accelerators, achieving a throughput of 1627 images per second and maintaining a top-1 accuracy of 70.95% on the ImageNet dataset.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。