提出重构方法，让概率电路在不同结构间高效转换并乘法。
Restructuring Tractable Probabilistic Circuits
- 设计通用重构算法，使电路适配目标vtree结构。
- 实现不同vtree电路的多项式时间乘法，效率显著提升。
- 适合需灵活推理的生成模型与可训练概率电路研究者。
概率电路（PCs）是支持高效推理的统一概率模型表示。许多应用如可控文本生成依赖于高效地对两个电路进行乘法运算。现有乘法算法要求电路遵循相同的结构，即变量作用域按同一vtree分解。本文提出并研究了结构化（-可分解）概率电路的重构任务，即变换一个结构化电路使其符合目标vtree。我们提出一种通用方法，证明其可导出多项式时间的电路乘法算法，适用于不同vtree的电路；同时开发了一种实用的深度缩减算法，在保持结构可分解性的同时减少网络深度。本工作为可计算概率推理开辟新路径，表明可在更宽松的结构下训练电路，并在推理时通过结构转换实现高效推理。
原文摘要 · Abstract (English)
Probabilistic circuits (PCs) are a unifying representation for probabilistic models that support tractable inference. Numerous applications of PCs like controllable text generation depend on the ability to efficiently multiply two circuits. Existing multiplication algorithms require that the circuits respect the same structure, i.e. variable scopes decomposes according to the same vtree. In this work, we propose and study the task of restructuring structured(-decomposable) PCs, that is, transforming a structured PC such that it conforms to a target vtree. We propose a generic approach for this problem and show that it leads to novel polynomial-time algorithms for multiplying circuits respecting different vtrees, as well as a practical depth-reduction algorithm that preserves structured decomposibility. Our work opens up new avenues for tractable PC inference, suggesting the possibility of training with less restrictive PC structures while enabling efficient inference by changing their structures at inference time.
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