用大模型加速模拟电路设计，通用性强且效率更高。
LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
- 结合大模型与优化算法，自动缩小电路设计空间。
- 在低复杂度电路上快2.15倍，高复杂度上性能提升48%。
- 无需额外训练，适配不同电路结构和工艺节点。
传统模拟电路设计耗时且依赖人工经验。现有自动化方法如贝叶斯优化（BO）和强化学习（RL）在跨电路拓扑与工艺节点时泛化能力差、成本高。本文提出LEDRO框架，利用大语言模型（LLM）结合优化技术，迭代精炼模拟电路尺寸设计空间。相比其他基于RL和BO的基线，LEDRO具有更强泛化性，无需针对不同拓扑或工艺节点进行设计标注或模型训练。我们在四个FinFET工艺节点上的22种运算放大器（Op-Amp）拓扑上进行了全面评估。结果表明，LEDRO平均性能提升13%（FoM），低复杂度电路实现2.15倍加速；高复杂度电路性能提升48%，加速1.7倍。充分验证了其高效性、有效性与可扩展性。
原文摘要 · Abstract (English)
Traditional approaches for designing analog circuits are time-consuming and require significant human expertise. Existing automation efforts using methods like Bayesian Optimization (BO) and Reinforcement Learning (RL) are sub-optimal and costly to generalize across different topologies and technology nodes. In our work, we introduce a novel approach, LEDRO, utilizing Large Language Models (LLMs) in conjunction with optimization techniques to iteratively refine the design space for analog circuit sizing. LEDRO is highly generalizable compared to other RL and BO baselines, eliminating the need for design annotation or model training for different topologies or technology nodes. We conduct a comprehensive evaluation of our proposed framework and baseline on 22 different Op-Amp topologies across four FinFET technology nodes. Results demonstrate the superior performance of LEDRO as it outperforms our best baseline by an average of 13% FoM improvement with 2.15x speed-up on low complexity Op-Amps and 48% FoM improvement with 1.7x speed-up on high complexity Op-Amps. This highlights LEDRO's effective performance, efficiency, and generalizability.
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