用大模型将电路网表自动转为可读的原理图，提升设计效率。
Schemato -- An LLM for Netlist-to-Schematic Conversion
- 基于大语言模型，将网表转换为LTSpice可用的文本格式原理图。
- 编译成功率达76%，连接准确性和结构相似性分别提升1.8倍和4.3倍。
- 适合需要快速生成可读电路图的模拟电路设计人员使用。
机器学习模型正在推动模拟电路设计的发展，但其生成的网表缺乏人类可读性。这带来了问题，因为人类设计师依赖原理图的可读性来直观理解、排查和优化电路。因此，为了有效融合领域知识，必须快速准确地将生成的网表转化为可解释的原理图。我们提出Schemato，一个用于网表到原理图转换的大语言模型。特别地，我们关注将网表转换为LTSpice使用的文本型原理图文件（.asc）。在自建电路数据集上的实验表明，Schemato的编译成功率达到76%，超过当前最优大模型的63%。此外，其生成原理图的平均图编辑距离和均方结构相似性指数（按编译成功率加权）分别比表现最佳的现有模型高出1.8倍和4.3倍，表明其生成的电路连接更准确，且与人工设计更接近。
原文摘要 · Abstract (English)
Machine learning models are advancing circuit design, particularly in analog circuits. They typically generate netlists that lack human interpretability. This is a problem as human designers heavily rely on the interpretability of circuit diagrams or schematics to intuitively understand, troubleshoot, and develop designs. Hence, to integrate domain knowledge effectively, it is crucial to translate ML-generated netlists into interpretable schematics quickly and accurately. We propose Schemato, a large language model (LLM) for netlist-to-schematic conversion. In particular, we consider our approach in converting netlists to .asc files, text-based schematic description used in LTSpice. Experiments on our circuit dataset show that Schemato achieves up to 76% compilation success rate, surpassing 63% scored by the state-of-the-art LLMs. Furthermore, our experiments show that Schemato generates schematics with an average graph edit distance score and mean structural similarity index measure, scaled by the compilation success rate that are 1.8x and 4.3x higher than the best performing LLMs respectively, demonstrating its ability to generate schematics that are more accurately connected and are closer to the reference human design.
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