用AI自动布局模拟芯片，提速降面积，工业级验证有效。
Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning
- 用关系图神经网络+强化学习自动规划电路布局
- 6个工业电路测试中，面积和布线长度均优于传统方法
- 适合需要快速迭代的模拟芯片设计团队
模拟集成电路（IC）布局通常依赖人工，由版图工程师手动安排元器件与模块位置。这一过程因布局与布线步骤相互依赖、存在大量电学与版图相关约束，以及高度定制化需求而复杂。本文提出一种基于强化学习的自动布局算法，结合关系图卷积神经网络对电路特征与位置约束进行编码。该组合模型可在不同拓扑与约束的电路间实现知识迁移，显著提升方案泛化能力。在6个工业电路上的应用表明，本方法在速度、面积和半周长布线长度方面均优于传统布局技术。集成至布局生成器后，整体布局时间减少67.3%，平均面积降低8.3%，相比人工布局表现优异。
原文摘要 · Abstract (English)
Analog integrated circuit (IC) floorplanning is typically a manual process with the placement of components (devices and modules) planned by a layout engineer. This process is further complicated by the interdependence of floorplanning and routing steps, numerous electric and layout-dependent constraints, as well as the high level of customization expected in analog design. This paper presents a novel automatic floorplanning algorithm based on reinforcement learning. It is augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints. The combination of these two machine learning methods enables knowledge transfer across different circuit designs with distinct topologies and constraints, increasing the \emph{generalization ability} of the solution. Applied to $6$ industrial circuits, our approach surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length. When integrated into a \emph{procedural generator} for layout completion, overall layout time was reduced by $67.3\%$ with a $8.3\%$ mean area reduction compared to manual layout.
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