用大模型自动设计更高效的加法器电路，面积减少3.7%。
PrefixLLM: LLM-aided Prefix Circuit Design
- 将电路设计转为结构化文本生成任务，用大模型自动构建有效电路表示
- 在相同延迟下，相比顶尖方法面积降低3.70%
- 适合集成电路设计、AI辅助硬件优化方向的研究者
前缀电路是数字加法器中的核心组件，因其在计算进位信号时的高效性而广泛应用于数字系统。实现面积与延迟最小化的前缀电路合成对提升现代计算系统的性能至关重要。近年来，大语言模型（LLMs）展现出惊人的文本生成能力。本文提出PrefixLLM，利用大模型进行前缀电路合成。PrefixLLM将前缀电路合成任务转化为结构化文本生成问题，称为结构化前缀电路表示（SPCR），并引入迭代框架，自动且准确地生成有效的SPCR。我们进一步提出了一个基于大模型的设计空间探索（DSE）框架，用于迭代搜索面积与延迟优化的前缀电路。与现有最先进方法相比，PrefixLLM在相同延迟约束下可将面积减少3.70%。本工作揭示了大模型在算术电路合成中的应用潜力，表明此类电路可被转化为结构化文本生成任务。
原文摘要 · Abstract (English)
Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with minimized area and delay is crucial for enhancing the performance of modern computing systems. Recently, large language models (LLMs) have demonstrated a surprising ability to perform text generation tasks. We propose PrefixLLM, that leverages LLMs for prefix circuit synthesis. PrefixLLM transforms the prefix circuit synthesis task into a structured text generation problem, termed the Structured Prefix Circuit Representation (SPCR), and introduces an iterative framework to automatically and accurately generate valid SPCRs. We further present a design space exploration (DSE) framework that uses LLMs to iteratively search for area and delay optimized prefix circuits. Compared to state-of-the-art, PrefixLLM can reduce the area by 3.70% under the same delay constraint. This work highlights the use of LLMs in the synthesis of arithmetic circuits, which can be transformed into the structured text generation.
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