用AI自动修正代码错误，让大模型生成的硬件代码更可靠
EDA-Aware RTL Generation with Large Language Models
- 构建多智能体系统，利用EDA工具报错反馈循环纠错
- 在VerilogEval-Human上功能通过率最高达77%，提升3.4倍
- 无需依赖特定大模型，适合想自动化生成正确硬件代码的人
大型语言模型（LLMs）在生成RTL代码方面日益流行，但在零样本设置下，即使最先进的模型也难以生成无错误代码，常需人工反复调试，显著增加验证工作量。为此，本文提出AIvril2，一个自验证、不依赖特定大模型的智能体框架，通过迭代修正语法和功能错误来提升RTL代码质量。该方法采用协作式多智能体系统，利用EDA工具生成的错误日志自动识别并修复设计缺陷。在VerilogEval-Human基准测试中，实验结果表明，该框架相比先前方法实现近3.4倍的性能提升；最佳情况下，Verilog和VHDL的功能通过率分别达到77%和66%，显著增强了基于大模型的RTL代码生成可靠性。
原文摘要 · Abstract (English)
Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, automated correction mechanisms to ensure code correctness from the start. In this work, we introduce AIvril2, a self-verifying, LLM-agnostic agentic framework aimed at enhancing RTL code generation through iterative corrections of both syntax and functional errors. Our approach leverages a collaborative multi-agent system that incorporates feedback from error logs generated by EDA tools to automatically identify and resolve design flaws. Experimental results, conducted on the VerilogEval-Human benchmark suite, demonstrate that our framework significantly improves code quality, achieving nearly a 3.4$\times$ enhancement over prior methods. In the best-case scenario, functional pass rates of 77% for Verilog and 66% for VHDL were obtained, thus substantially improving the reliability of LLM-driven RTL code generation.
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