用分层结构让大模型生成更可靠的硬件代码。
HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
- 将复杂电路分解为可管理的模块，由大模型逐层生成。
- 通过自动设计空间探索提升生成质量，减少错误。
- 支持人机交互和代码复用，适合芯片设计初学者。
近期大型语言模型（LLMs）在代码生成方面表现出色，将其能力拓展至硬件描述语言（HDL）颇具前景。然而，现有方法通常生成单一代码块，难以构建分层结构，尤其在领域专用加速器（DSAs）等复杂设计中易出现幻觉。为此，我们提出HiVeGen——一种基于分层结构的Verilog生成框架，将生成任务分解为层级化子模块，使大模型可管理。该框架进一步利用分层结构优势：在提示生成中引入层次感知的设计空间探索（DSE），采用基于权重的检索机制增强代码复用，并支持实时人机交互以降低纠错成本，显著提升生成设计的质量。
原文摘要 · Abstract (English)
With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.
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