提出可自适应调整电压的电荷域存内计算芯片，提升边缘AI能效与精度。
IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping
- 通过动态电压调节和数据分布感知重整形，避免传统固定电压导致的精度损失。
- 实测8位系统能效达40TOPS/W，峰值能效0.15-8POPS/W，超越前人3-5倍。
- 适合低功耗边缘设备部署，尤其适用于对能效敏感的嵌入式深度学习任务。
电荷域存内计算SRAM近年来成为处理边缘端子8比特以下卷积神经网络的高效高精度折中方案。然而，现有方法普遍采用固定点积电压摆幅，因数据相关截断或舍入导致有效模数转换位数下降，浪费转换能量并损害计算精度。为此，本文提出基于22nm FD-SOI工艺的1至8比特自适应电荷域存内计算加速器IMAGINE，采用1152×256端到端电荷基宏，通过输入串行、权重并行累加实现多比特点积，避免高功耗数模转换器。通过通道级点积阵列拆分与线性模拟批归一化（ABN）实现动态电压调节，达成分布感知的数据重整形。关键设计约束通过在存内计算感知的CNN训练框架中引入后硅等效噪声得以缓解。实测结果表明，8比特系统级能效达40TOPS/W（0.3/0.6V），在MNIST与CIFAR-10上保持优异精度。该宏区域能效峰值达0.15-8POPS/W，面积能效最高达2.6-154TOPS/mm²，随8至1比特计算精度动态扩展。相较此前电荷基设计提升3至5倍，且为首个实现线性存内缩放的工作。
原文摘要 · Abstract (English)
Charge-domain compute-in-memory (CIM) SRAMs have recently become an enticing compromise between computing efficiency and accuracy to process sub-8b convolutional neural networks (CNNs) at the edge. Yet, they commonly make use of a fixed dot-product (DP) voltage swing, which leads to a loss in effective ADC bits due to data-dependent clipping or truncation effects that waste precious conversion energy and computing accuracy. To overcome this, we present IMAGINE, a workload-adaptive 1-to-8b CIM-CNN accelerator in 22nm FD-SOI. It introduces a 1152x256 end-to-end charge-based macro with a multi-bit DP based on an input-serial, weight-parallel accumulation that avoids power-hungry DACs. An adaptive swing is achieved by combining a channel-wise DP array split with a linear in-ADC implementation of analog batch-normalization (ABN), obtaining a distribution-aware data reshaping. Critical design constraints are relaxed by including the post-silicon equivalent noise within a CIM-aware CNN training framework. Measurement results showcase an 8b system-level energy efficiency of 40TOPS/W at 0.3/0.6V, with competitive accuracies on MNIST and CIFAR-10. Moreover, the peak energy and area efficiencies of the 187kB/mm2 macro respectively reach up to 0.15-8POPS/W and 2.6-154TOPS/mm2, scaling with the 8-to-1b computing precision. These results exceed previous charge-based designs by 3-to-5x while being the first work to provide linear in-memory rescaling.
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