用阻变存储器自带噪声实现神经网络激活，省去数模转换器。
A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
- 利用阻变器件噪声实现随机二值化神经元，替代传统激活计算
- 去除数模/模数转换器，能效提升显著，推理精度无损
- 适合低功耗边缘AI芯片设计，尤其关注能效的场景
基于阻变存储器（ReRAM）的加速器通过存内模拟计算实现超低功耗神经网络处理。然而，外围电路开销大和复杂的非线性激活方式限制了系统能效的进一步提升。本文提出一种全硬件实现的新型方案，利用ReRAM器件固有的采样噪声信号，实现神经网络中Sigmoid与SoftMax激活函数的随机效应。所提出的ReRAM模拟计算加速器（RACA）通过结合随机二值化神经元与ReRAM交叉阵列，完全消除数字-模拟转换器（DAC）和模拟-数字转换器（ADC）以及显式激活函数计算单元带来的能效与面积损耗。实验结果表明，该设计在不牺牲推理精度的前提下，全面优于传统架构的各项性能指标。
原文摘要 · Abstract (English)
Emerging ReRAM-based accelerators process neural networks via analog Computing-in-Memory (CiM) for ultra-high energy efficiency. However, significant overhead in peripheral circuits and complex nonlinear activation modes constrain system energy efficiency improvements. This work explores the hardware implementation of the Sigmoid and SoftMax activation functions of neural networks with stochastically binarized neurons by utilizing sampled noise signals from ReRAM devices to achieve a stochastic effect. We propose a complete ReRAM-based Analog Computing Accelerator (RACA) that accelerates neural network computation by leveraging stochastically binarized neurons in combination with ReRAM crossbars. The novel circuit design removes significant sources of energy/area efficiency degradation, i.e., the Digital-to-Analog and Analog-to-Digital Converters (DACs and ADCs) as well as the components to explicitly calculate the activation functions. Experimental results show that our proposed design outperforms traditional architectures across all overall performance metrics without compromising inference accuracy.
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