用图神经网络实现可迁移的芯片全局布局，提升效率与性能。
TransPlace: Transferable Circuit Global Placement via Graph Neural Network
- 构建网表图与位置编码，学习平移旋转不变表示
- 在未见过电路上实现1.2倍加速，拥塞降低30%
- 适合大规模芯片设计，尤其关注布局效率的工程师
全局布局是芯片物理设计中的关键步骤，直接影响芯片性能。传统方法对每个电路独立从头优化，忽视可迁移知识，导致复杂度上升时效率与性能受限。本文提出TransPlace框架，通过图神经网络在连续空间中学习百万级异尺寸单元的布局。其创新包括：i) 使用网表图高效建模电路拓扑；ii) 引入单元流与相对位置编码，学习SE(2)不变表示；iii) 设计定制化图神经网络，实现布局知识的有信息参数化；iv) 采用粗到精的两阶段布局策略。相比现有最优方法，基于少量高质量布局训练的TransPlace，在未见电路上实现1.2倍速度提升，拥塞降低30%，时序改善9%，布线长度减少5%。
原文摘要 · Abstract (English)
Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance. Prior global placement methods optimize each circuit design individually from scratch. Their neglect of transferable knowledge limits solution efficiency and chip performance as circuit complexity drastically increases. This study presents TransPlace, a global placement framework that learns to place millions of mixed-size cells in continuous space. TransPlace introduces i) Netlist Graph to efficiently model netlist topology, ii) Cell-flow and relative position encoding to learn SE(2)-invariant representation, iii) a tailored graph neural network architecture for informed parameterization of placement knowledge, and iv) a two-stage strategy for coarse-to-fine placement. Compared to state-of-the-art placement methods, TransPlace-trained on a few high-quality placements-can place unseen circuits with 1.2x speedup while reducing congestion by 30%, timing by 9%, and wirelength by 5%.
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