构建虚拟机与FPGA硬件协同仿真框架，加速数据中心加速器开发调试。
A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs
- 在虚拟机中同步运行主机软件与FPGA硬件设计，实现真实系统级仿真。
- 支持操作系统与驱动直接运行，避免因修改导致系统挂死。
- 提供完整可观测性，将调试迭代时间缩短至分钟级，适合硬件/软件联合开发人员。
PCIe连接的FPGA正成为数据中心加速器的主流技术。然而，主机软件与FPGA硬件的联合开发与调试面临挑战：硬件设计改动需耗时的FPGA综合流程，而软件修改（尤其是操作系统和设备驱动）常导致系统挂起且缺乏足够调试信息。上述问题造成冗长的调试循环与缓慢的开发进程。为此，我们设计了一种VM-HDL协同仿真框架，可在虚拟环境中完整运行与目标物理系统相同的软件、操作系统及硬件设计，同时提供全链路可见性，并显著缩短调试周期。
原文摘要 · Abstract (English)
PCIe-connected FPGAs are gaining popularity as an accelerator technology in data centers. However, it is challenging to jointly develop and debug host software and FPGA hardware. Changes to the hardware design require a time-consuming FPGA synthesis process, and modification to the software, especially the operating system and device drivers, can frequently cause the system to hang, without providing enough information for debugging. The combination of these problems results in long debug iterations and a slow development process. To overcome these problems, we designed a VM-HDL co-simulation framework, which is capable of running the same software, operating system, and hardware designs as the target physical system, while providing full visibility and significantly shorter debug iterations.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。