用无线连接提升多芯片AI加速器性能，最高提速20%。
Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators
- 用无线技术补充传统有线互连，提升多芯片架构灵活性。
- 平均提速10%，峰值提速达20%。
- 适合追求高吞吐、低延迟的AI硬件设计者。
人工智能工作负载对计算能力的需求持续增长，推动产业开发更快更高效的加速器。然而，定制硬件的僵化特性与可扩展、多功能架构的需求相矛盾，难以适应不断演进且异构的机器学习模型。在此背景下，集成多个（可能异构）加速器的多芯片组架构虽具吸引力，却受限于仍僵化且低效的芯片间互连。本文探索无线技术作为现有有线互连的补充，在多芯片组方案中的潜力。基于前沿评估框架，我们发现无线互连可带来平均10%的加速，最大达20%。同时强调了有线与无线互连间负载均衡的重要性，这将在未来工作中进一步研究。
原文摘要 · Abstract (English)
The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflicts with the need for scalable and versatile architectures capable of catering to the needs of the evolving and heterogeneous pool of Machine Learning (ML) models in the literature. In this context, multi-chiplet architectures assembling multiple (perhaps heterogeneous) accelerators are an appealing option that is unfortunately hindered by the still rigid and inefficient chip-to-chip interconnects. In this paper, we explore the potential of wireless technology as a complement to existing wired interconnects in this multi-chiplet approach. Using an evaluation framework from the state-of-the-art, we show that wireless interconnects can lead to speedups of 10% on average and 20% maximum. We also highlight the importance of load balancing between the wired and wireless interconnects, which will be further explored in future work.
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