arXiv:2502.00026cs.ARcs.AI2025-02AAAI被引 3

用新型块浮点优化大模型非线性计算,显著提速且几乎不损失精度。

Pushing the Limits of BFP on Narrow Precision LLM Inference

  • 提出DBFP块浮点新格式,自适应分组与聚焦策略应对数据多样性。
  • 在LLaMA的Softmax上实现74%的GPU加速,较先进设计提升10倍性能开销比。
  • 软硬件协同设计,适用于FPGA和ASIC,适合部署高并发大模型推理。

大型语言模型(LLMs)的庞大计算与内存需求限制了其实际部署。块浮点(BFP)已被证明可有效加速线性运算,而线性运算是LLM工作负载的核心。然而,随着序列长度增加,注意力等非线性运算因二次复杂度逐渐成为性能瓶颈,且主要依赖低效浮点格式执行,导致软件效率与硬件开销难以优化。本文深入研究将BFP应用于非线性运算的局限与潜力,提出硬件-软件协同设计框架DB-Attn:(i) DBFP,一种改进的BFP格式,采用枢纽聚焦策略应对多样数据,并通过自适应分组实现灵活指数共享;(ii) DH-LUT,专为加速非线性运算设计的新查表算法;(iii) 实现基于DBFP的RTL级引擎,支持FPGA与ASIC。实验表明,DB-Attn在几乎无精度损失下带来显著性能提升,在LLaMA的Softmax上达到74%的GPU加速,相较最先进设计实现10倍低开销性能提升。

原文摘要 · Abstract (English)

The substantial computational and memory demands of Large Language Models (LLMs) hinder their deployment. Block Floating Point (BFP) has proven effective in accelerating linear operations, a cornerstone of LLM workloads. However, as sequence lengths grow, nonlinear operations, such as Attention, increasingly become performance bottlenecks due to their quadratic computational complexity. These nonlinear operations are predominantly executed using inefficient floating-point formats, which renders the system challenging to optimize software efficiency and hardware overhead. In this paper, we delve into the limitations and potential of applying BFP to nonlinear operations. Given our findings, we introduce a hardware-software co-design framework (DB-Attn), including: (i) DBFP, an advanced BFP version, overcomes nonlinear operation challenges with a pivot-focus strategy for diverse data and an adaptive grouping strategy for flexible exponent sharing. (ii) DH-LUT, a novel lookup table algorithm dedicated to accelerating nonlinear operations with DBFP format. (iii) An RTL-level DBFP-based engine is implemented to support DB-Attn, applicable to FPGA and ASIC. Results show that DB-Attn provides significant performance improvements with negligible accuracy loss, achieving 74% GPU speedup on Softmax of LLaMA and 10x low overhead performance improvement over SOTA designs.

大模型推理块浮点硬件加速FPGA

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