InTAR动态切换计算模式，高效应对深度学习任务间数据量波动。
InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs
- 根据任务规模自动切换串行与数据流执行模式，减少内存开销
- 相比传统加速器，速度提升1.8至7.1倍，复杂模型快3.65至39.14倍
- 适合需快速重构的FPGA部署场景，支持高层次综合快速开发
深度神经网络（DNN）的发展带来对算力和内存的更高需求。现代DNN在不同任务间表现出显著的数据量波动（HDV），对FPGA加速构成挑战：传统加速器依赖固定执行模式（数据流或串行），易引发流水线阻塞或频繁访问片外内存。为此，我们提出跨任务自重构加速器（InTAR），一种针对FPGA上HDV应用的新设计方法。InTAR结合了串行执行的高效率与数据流执行的低内存开销，基于资源约束和问题规模，在电路设计前静态确定重构调度，实现自动模式切换。不同于以往可重构加速器，InTAR在设计阶段编码重构方案，支持仅分配必要逻辑与互连，从而实现高时钟频率、少资源占用及低重构延迟。此外，InTAR兼容HLS等高层工具，支持快速设计生成。我们在多个多任务HDV DNN核上实现了InTAR，相比数据流和串行加速器分别获得1.8×和7.1×性能提升。进一步扩展至GPT-2 medium，其在FPGA上比现有最优加速器（Allo和DFX）快1.72~10.44×，并节省1.72~10.44×的DSP资源；功耗效率较GPU提升1.66~7.17×。
原文摘要 · Abstract (English)
The rise of deep neural networks (DNNs) has driven an increased demand for computing power and memory. Modern DNNs exhibit high data volume variation (HDV) across tasks, which poses challenges for FPGA acceleration: conventional accelerators rely on fixed execution patterns (dataflow or sequential) that can lead to pipeline stalls or necessitate frequent off-chip memory accesses. To address these challenges, we introduce the Inter-Task Auto-Reconfigurable Accelerator (InTAR), a novel accelerator design methodology for HDV applications on FPGAs. InTAR combines the high computational efficiency of sequential execution with the reduced off-chip memory overhead of dataflow execution. It switches execution patterns automatically with a static schedule determined before circuit design based on resource constraints and problem sizes. Unlike previous reconfigurable accelerators, InTAR encodes reconfiguration schedules during circuit design, allowing model-specific optimizations that allocate only the necessary logic and interconnects. Thus, InTAR achieves a high clock frequency with fewer resources and low reconfiguration time. Furthermore, InTAR supports high-level tools such as HLS for fast design generation. We implement a set of multi-task HDV DNN kernels using InTAR. Compared with dataflow and sequential accelerators, InTAR exhibits $\mathbf{1.8\times}$ and $\mathbf{7.1 \times}$ speedups correspondingly. Moreover, we extend InTAR to GPT-2 medium as a more complex example, which is $\mathbf{3.65 \sim 39.14\times}$ faster and a $\mathbf{1.72 \sim 10.44\times}$ more DSP efficient than SoTA accelerators (Allo and DFX) on FPGAs. Additionally, this design demonstrates $\mathbf{1.66 \sim 7.17\times}$ better power efficiency than GPUs. Code: https://github.com/OswaldHe/InTAR
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