DICE首次实现模拟与数字电路的设备级图神经网络预训练，提升电路设计效率。
DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining
- 基于图对比学习，无需仿真即可预训练电路图模型。
- 在三个下游任务中显著提升性能，适用于模拟与数字电路。
- 创新性引入两种图增强技术，支持跨类型电路建模。
通过无监督图表示学习，预训练模型在社交网络分析、分子设计和电子设计自动化（EDA）等领域取得了显著进展。然而，现有EDA研究主要集中于数字电路的预训练，忽视了模拟与混合信号电路。为此，我们提出DICE，首个专为模拟与数字电路设计的设备级集成电路编码器，基于自监督学习的图神经网络（GNN），用于图级别预测任务。DICE采用无需仿真的预训练方法，基于图对比学习，并引入两种新颖的图增强技术。实验结果表明，在三个下游任务中均实现显著性能提升，验证了DICE在模拟与数字电路中的有效性。代码已开源：github.com/brianlsy98/DICE。
原文摘要 · Abstract (English)
Pretraining models with unsupervised graph representation learning has led to significant advancements in domains such as social network analysis, molecular design, and electronic design automation (EDA). However, prior work in EDA has mainly focused on pretraining models for digital circuits, overlooking analog and mixed-signal circuits. To bridge this gap, we introduce DICE, a Device-level Integrated Circuits Encoder, which is the first graph neural network (GNN) pretrained via self-supervised learning specifically tailored for graph-level prediction tasks in both analog and digital circuits. DICE adopts a simulation-free pretraining approach based on graph contrastive learning, leveraging two novel graph augmentation techniques. Experimental results demonstrate substantial performance improvements across three downstream tasks, highlighting the effectiveness of DICE for both analog and digital circuits. The code is available at github.com/brianlsy98/DICE.
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