用强化学习自动发现处理器瞬时执行漏洞,效率远超传统方法。
μRL: Discovering Transient Execution Vulnerabilities Using Reinforcement Learning
- 通过强化学习智能探索指令序列,实时反馈引导漏洞发现。
- 在Intel Skylake-X和Raptor Lake上成功触发字节泄露,无需异常中断。
- 可适应不同处理器架构,适合硬件安全研究人员使用。
我们提出利用强化学习解决发现微架构漏洞(如Spectre、Meltdown)的挑战,这些漏洞源于现代处理器中细微的交互行为。传统方法如随机模糊测试难以高效探索庞大的指令空间,常错过特定条件下的漏洞。为此,我们设计了一种基于反馈的智能方法:强化学习代理与处理器交互,依据实时反馈优先生成更可能暴露漏洞的指令序列,显著提升发现效率。实验表明,该系统能有效适应多种微架构,具备跨代可扩展性。通过自动化探索,减少人工干预,实现持续学习以发现隐藏漏洞。此外,该方法能检测到微妙信号,如时间异常或异常缓存行为,提示微架构缺陷。在Intel Skylake-X和Raptor Lake上,我们的强化学习代理成功生成导致显著可观测字节泄露的指令序列,且未触发任何μcode协助、故障或中断。新发现的泄漏序列涉及多种Intel指令,包括SERIALIZE、VERR/VERW、CLMUL、MMX-x87转换、LSL+RDSCP和LAR。初步结果验证了该方法的有效性。
原文摘要 · Abstract (English)
We propose using reinforcement learning to address the challenges of discovering microarchitectural vulnerabilities, such as Spectre and Meltdown, which exploit subtle interactions in modern processors. Traditional methods like random fuzzing fail to efficiently explore the vast instruction space and often miss vulnerabilities that manifest under specific conditions. To overcome this, we introduce an intelligent, feedback-driven approach using RL. Our RL agents interact with the processor, learning from real-time feedback to prioritize instruction sequences more likely to reveal vulnerabilities, significantly improving the efficiency of the discovery process. We also demonstrate that RL systems adapt effectively to various microarchitectures, providing a scalable solution across processor generations. By automating the exploration process, we reduce the need for human intervention, enabling continuous learning that uncovers hidden vulnerabilities. Additionally, our approach detects subtle signals, such as timing anomalies or unusual cache behavior, that may indicate microarchitectural weaknesses. This proposal advances hardware security testing by introducing a more efficient, adaptive, and systematic framework for protecting modern processors. When unleashed on Intel Skylake-X and Raptor Lake microarchitectures, our RL agent was indeed able to generate instruction sequences that cause significant observable byte leakages through transient execution without generating any $μ$code assists, faults or interrupts. The newly identified leaky sequences stem from a variety of Intel instructions, e.g. including SERIALIZE, VERR/VERW, CLMUL, MMX-x87 transitions, LSL+RDSCP and LAR. These initial results give credence to the proposed approach.
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