用图信号处理加速芯片布局，免训练且提速45%以上
The Power of Graph Signal Processing for Chip Placement Acceleration
- 基于图信号处理，无需训练直接生成优化布局
- 相比DREAMPlace，总运行时间提升超45%
- 适合追求高效布局的集成电路设计人员
布局是超大规模集成电路物理设计中计算复杂度极高的关键任务。现代解析式布局器将布局目标建模为非线性优化问题，迭代耗时长。近年来研究转向基于深度学习的方法，尤其是图卷积网络（GCNs），但这类方法因电路布局规模大、设计特异性图统计复杂，需大量时间和数据进行模型训练。本文提出GiFt，一种基于图信号处理的无参数加速布局技术。GiFt能有效捕捉电路图的多分辨率平滑信号，无需训练即可生成优化布局，并显著减少解析式布局器的迭代次数。实验结果表明，GiFt大幅提升了布局效率，同时性能达到或优于现有最优布局器。特别是相比最近提出的GPU加速解析式布局器DREAMPlace，GF-Placer在总运行时间上提升超过45%。
原文摘要 · Abstract (English)
Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%.
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