AMPLE用事件驱动加速图神经网络混合精度推理，性能远超传统硬件。
AMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks
- 采用事件驱动架构，动态响应节点计算需求
- 支持节点级混合精度量化，提升计算效率
- 适合需要低延迟图计算的部署场景
图神经网络（GNN）因其在非欧几里得数据上的优异表现而受到关注。由于图结构稀疏导致内存访问不规则，定制硬件对GNN尤为有益。然而，现有FPGA加速器受限于双缓冲机制，无法适应典型图数据集中的不规则节点分布。为此，我们提出AMPLE（加速消息传递逻辑引擎），一种基于新型事件驱动编程范式的FPGA加速器。设计了混合精度架构，实现节点级粒度的量化。同时，引入数据与指令预取机制，优化片外内存访问并最大化节点并行性。在包含2K至700K节点的引用和社交媒体图数据集上评估显示，平均相比CPU快243倍，相比GPU快7.2倍。
原文摘要 · Abstract (English)
Graph Neural Networks (GNNs) have recently gained attention due to their performance on non-Euclidean data. The use of custom hardware architectures proves particularly beneficial for GNNs due to their irregular memory access patterns, resulting from the sparse structure of graphs. However, existing FPGA accelerators are limited by their double buffering mechanism, which doesn't account for the irregular node distribution in typical graph datasets. To address this, we introduce \textbf{AMPLE} (Accelerated Message Passing Logic Engine), an FPGA accelerator leveraging a new event-driven programming flow. We develop a mixed-arithmetic architecture, enabling GNN inference to be quantized at a node-level granularity. Finally, prefetcher for data and instructions is implemented to optimize off-chip memory access and maximize node parallelism. Evaluation on citation and social media graph datasets ranging from $2$K to $700$K nodes showed a mean speedup of $243\times$ and $7.2\times$ against CPU and GPU counterparts, respectively.
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