用机器学习预测FPGA配置资源用量，减少试错次数。
AI-Driven Optimization of Hardware Overlay Configurations
- 用随机森林回归分析历史数据，预估配置资源占用。
- 预测逻辑单元、分布式存储和扇出数，误差小且高效。
- 适合硬件设计者快速筛选最优配置，加速开发流程。
FPGA叠加层的设计与优化过程复杂且耗时，通常需多次试错才能确定合适配置。本文提出一种基于人工智能的FPGA叠加层配置优化方法，聚焦于ZCU104 FPGA上的NAPOLY+自动机处理器。通过机器学习技术，特别是随机森林回归，我们在硬件编译前预测不同配置的可行性和效率。该方法基于历史设计数据，估算逻辑元件、分布式内存及扇出数等资源利用率。实验结果表明，模型预测精度高，与实际资源使用量高度吻合，显著减少了所需迭代次数，加快了设计进程。
原文摘要 · Abstract (English)
Designing and optimizing FPGA overlays is a complex and time-consuming process, often requiring multiple trial-and-error iterations to determine a suitable configuration. This paper presents an AI-driven approach to optimizing FPGA overlay configurations, specifically focusing on the NAPOLY+ automata processor implemented on the ZCU104 FPGA. By leveraging machine learning techniques, particularly Random Forest regression, we predict the feasibility and efficiency of different configurations before hardware compilation. Our method significantly reduces the number of required iterations by estimating resource utilization, including logical elements, distributed memory, and fanout, based on historical design data. Experimental results demonstrate that our model achieves high prediction accuracy, closely matching actual resource usage while accelerating the design process.
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