用仿生耳模型加速时间序列分类，低延迟低功耗
Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA
- 用人工耳模型将时序信号转为稀疏事件数据，减少计算量
- 在SHD数据集上达92.7%准确率，参数比顶尖模型少67%
- 适合边缘设备实时处理，硬件加速降低延迟和资源占用
随着嵌入式边缘传感器记录的数据量增长，本地智能处理需求日益增加。这类数据多为时序信号，可通过AI模型实现本地实时预测。但需兼顾低延迟与低功耗的软硬件协同方案。本文提出一种面向时序分类的事件图神经网络硬件实现。利用人工耳模型将输入时序信号转换为稀疏事件数据格式，使事件图相比其他AI方法大幅减少计算量。设计在SoC FPGA上实现，并应用于Spiking Heidelberg Digits（SHD）数据集的实时处理，以评估性能。基础模型在SHD上达到92.7%浮点精度，较当前最优模型分别低2.4%和2%，但模型参数分别减少超过10%和67%。量化模型达92.3%准确率，较基于FPGA的脉冲神经网络实现提升19.3%和4.5%，同时使用更少计算资源并降低延迟。
原文摘要 · Abstract (English)
As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10% and 67% fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency.
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