提出高效可扩展的VLSI全局布线方法，有效避开障碍物并降低布线成本。
A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow
- 基于规则的障碍避让矩形斯坦纳树算法，快速生成避障布线拓扑
- 在基准测试中消除障碍违规，线长和溢出成本显著降低
- 适合处理含复杂障碍物的大规模集成电路设计
布线是VLSI设计流程中的关键步骤。随着制造技术进步，设计规则中出现更多约束，尤其是布线过程中的障碍物问题，导致布线复杂度上升。然而，许多全局布线器因缺乏可扩展的避障树生成方法，难以高效生成无障碍解，尤其在现代具有复杂障碍物和网表的设计中表现不佳。本文提出一种面向障碍物的高效VLSI全局布线流程。该流程在树生成阶段采用基于规则的障碍避让矩形斯坦纳最小树（OARSMT）算法，兼具可扩展性与高效性，能在早期阶段生成避障拓扑。后续阶段引入基于OARSMT引导的稀疏迷宫布线，进一步减少障碍违规和溢出成本。与先进方法相比，本方法在基准测试中成功消除障碍违规，降低线长和溢出成本，仅牺牲少量过孔数和运行时间开销。
原文摘要 · Abstract (English)
Routing is a crucial step in the VLSI design flow. With the advancement of manufacturing technologies, more constraints have emerged in design rules, particularly regarding obstacles during routing, leading to increased routing complexity. Unfortunately, many global routers struggle to efficiently generate obstacle-free solutions due to the lack of scalable obstacle-avoiding tree generation methods and the capability of handling modern designs with complex obstacles and nets. In this work, we propose an efficient obstacle-aware global routing flow for VLSI designs with obstacles. The flow includes a rule-based obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) algorithm during the tree generation phase. This algorithm is both scalable and fast to provide tree topologies avoiding obstacles in the early stage globally. With its guidance, OARSMT-guided and obstacle-aware sparse maze routing are proposed in the later stages to minimize obstacle violations further and reduce overflow costs. Compared to advanced methods on the benchmark with obstacles, our approach successfully eliminates obstacle violations, and reduces wirelength and overflow cost, while sacrificing only a limited number of via counts and runtime overhead.
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