提出基于路径的高效布线框架，显著提升芯片时序优化效果。
Timing-Driven Global Placement by Efficient Critical Path Extraction
- 通过GPU加速提取关键路径，融合路径级时序信息。
- 平均降低40.5%总负松弛，改善8.3%最差负松弛。
- 适合追求高精度时序优化的集成电路设计工程师。
集成电路全局布线中的时序优化是数十年来的研究重点，但仍未完全解决。现有解析方法多使用引脚级时序信息调整网络权重，虽快速简单，却忽略了时序图的路径本质。传统路径级方法因关键路径数量指数增长，难以兼顾准确与效率。本文提出一种基于GPU加速的时序驱动全局布线框架，将精确的路径级信息集成至高效的DREAMPlace架构中，优化细粒度引脚间吸引目标，并借助高效的临界路径提取技术实现。我们还设计了一种与RC时序模型匹配的二次距离损失函数。实验表明，该方法显著优于当前领先的时序驱动布线器，在总负松弛（TNS）上平均提升40.5%，最差负松弛（WNS）提升8.3%，同时改善了半周长线长（HPWL）。
原文摘要 · Abstract (English)
Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical methods typically use pin-level timing information to adjust net weights, which is fast and simple but neglects the path-based nature of the timing graph. The existing path-based methods, however, cannot balance the accuracy and efficiency due to the exponential growth of number of critical paths. In this work, we propose a GPU-accelerated timing-driven global placement framework, integrating accurate path-level information into the efficient DREAMPlace infrastructure. It optimizes the fine-grained pin-to-pin attraction objective and is facilitated by efficient critical path extraction. We also design a quadratic distance loss function specifically to align with the RC timing model. Experimental results demonstrate that our method significantly outperforms the current leading timing-driven placers, achieving an average improvement of 40.5% in total negative slack (TNS) and 8.3% in worst negative slack (WNS), as well as an improvement in half-perimeter wirelength (HPWL).
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