提出稀疏连接优化方法，提升FPGA上查表型神经网络的精度与效率。
SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networks
- 基于非贪婪策略动态剪枝并重连关键连接，实现高效稀疏化。
- 在MNIST上精度提升2.13%，杰特粒子分类任务提升0.94%。
- 无需硬件改动，适合部署于资源受限的FPGA设备。
在如现场可编程门阵列（FPGA）等资源受限边缘设备上部署深度神经网络（DNN），需在延迟、功耗与资源占用之间取得平衡，同时保持高精度。现有基于查表（LUT）的DNN模型（如LogicNets、PolyLUT、PolyLUT-Add、NeuraLUT）利用FPGA原生资源实现随机稀疏连接。本文提出SparseLUT，一种面向查表型DNN的以连接性为中心的训练优化技术。该方法采用非贪婪训练策略，优先剪除不重要连接，并有策略地重建替代连接，从而高效收敛至目标稀疏度。实验表明，各类基准测试中精度均稳定提升，包括在MNIST上最高达2.13%的增益，以及在杰特粒子结构分类任务中0.94%的改进。该方法无硬件开销，且达到当前查表型DNN的最优性能。
原文摘要 · Abstract (English)
The deployment of deep neural networks (DNNs) on resource-constrained edge devices such as field-programmable gate arrays (FPGAs) requires a careful balance of latency, power, and resource usage while maintaining high accuracy. Existing Lookup Table (LUT)-based DNNs, including LogicNets, PolyLUT, PolyLUT-Add, and NeuraLUT, exploit native FPGA resources with random sparse connectivity. This paper introduces SparseLUT, a connectivity-centric training technique tailored for LUT-based DNNs. SparseLUT leverages a non-greedy training strategy that prioritizes the pruning of less significant connections and strategically regrows alternative ones, resulting in efficient convergence to the target sparsity. Experimental results show consistent accuracy improvements across benchmarks, including up to a 2.13\% increase on MNIST and a 0.94\% improvement for Jet Substructure Classification compared to random sparsity. This is done without any hardware overhead and achieves state-of-the-art results for LUT-based DNNs.
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