开源3D集成电路后端评估平台，可全面评测功耗性能面积热特性。
Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation
- 基于OpenROAD框架构建模块化3D设计流程，支持分区、布局、布线等环节
- 相比2D流程，面积减少51.19%，线长降低24.06%，时序改善30.84%
- 提供可复现的基准测试环境，适合研究3D EDA算法与商业工具对比
本文提出Open3DBench，一个基于OpenROAD-flow-scripts框架的开源3D-IC后端实现基准测试平台，支持对功耗、性能、面积和热特性的全面评估。该流程支持3D分区、布局、3D布线、RC提取和热仿真等模块化集成，与依赖商用工具和内部脚本的先进3D设计流程对齐。我们提出了两种基础3D布局算法：Open3D-Tiling注重规则宏放置，Open3D-DMP通过与分析式布局器DREAMPlace的跨晶粒协同布局优化线长。实验表明，相比2D流程，面积减少51.19%，线长降低24.06%，时序改善30.84%，功耗下降5.72%。结果还显示，线长优化并不必然带来PPA提升，强调需发展以PPA为导向的方法。Open3DBench为评估3D EDA方法提供了标准化、可复现的平台，有效弥合了开源工具与商业解决方案在3D-IC设计间的差距。
原文摘要 · Abstract (English)
This work introduces Open3DBench, an open-source 3D-IC backend implementation benchmark built upon the OpenROAD-flow-scripts framework, enabling comprehensive evaluation of power, performance, area, and thermal metrics. Our proposed flow supports modular integration of 3D partitioning, placement, 3D routing, RC extraction, and thermal simulation, aligning with advanced 3D flows that rely on commercial tools and in-house scripts. We present two foundational 3D placement algorithms: Open3D-Tiling, which emphasizes regular macro placement, and Open3D-DMP, which enhances wirelength optimization through cross-die co-placement with analytical placer DREAMPlace. Experimental results show significant improvements in area (51.19%), wirelength (24.06%), timing (30.84%), and power (5.72%) compared to 2D flows. The results also highlight that better wirelength does not necessarily lead to PPA gain, emphasizing the need of developing PPA-driven methods. Open3DBench offers a standardized, reproducible platform for evaluating 3D EDA methods, effectively bridging the gap between open-source tools and commercial solutions in 3D-IC design.
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