用推测解码提升Verilog代码生成速度与质量。
Speculative Decoding for Verilog: Speed and Quality, All in One
- 按语法结构对齐解码停点，优化令牌化。
- 生成速度最高提升5.05倍，准确率提高17.19%。
- 适合需要高效高质硬件描述代码生成的场景。
大语言模型（LLM）的快速发展已革新多种编程语言的代码生成任务。然而，像Verilog这类具有特定语法且训练数据较少的编程语言，传统分词和解码方法面临挑战。本文首次将推测解码应用于Verilog代码生成，实现速度与质量的双重提升。不同于常规分词方式导致语义结构碎片化，我们的方法使解码停点与语法重要标记对齐，更利于模型学习令牌分布，有效解决分词缺陷，增强对Verilog逻辑结构的捕捉能力。实验表明，该方法在RTLLM上使生成速度最高提升5.05倍，pass@10功能准确率最高提升17.19%，显著缩小专用语言代码生成的质量差距。结果表明，推测解码是提升特定编程语言代码生成性能的有力方案。
原文摘要 · Abstract (English)
The rapid advancement of large language models (LLMs) has revolutionized code generation tasks across various programming languages. However, the unique characteristics of programming languages, particularly those like Verilog with specific syntax and lower representation in training datasets, pose significant challenges for conventional tokenization and decoding approaches. In this paper, we introduce a novel application of speculative decoding for Verilog code generation, showing that it can improve both inference speed and output quality, effectively achieving speed and quality all in one. Unlike standard LLM tokenization schemes, which often fragment meaningful code structures, our approach aligns decoding stops with syntactically significant tokens, making it easier for models to learn the token distribution. This refinement addresses inherent tokenization issues and enhances the model's ability to capture Verilog's logical constructs more effectively. Our experimental results show that our method achieves up to a 5.05x speedup in Verilog code generation and increases pass@10 functional accuracy on RTLLM by up to 17.19% compared to conventional training strategies. These findings highlight speculative decoding as a promising approach to bridge the quality gap in code generation for specialized programming languages.
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