提出快速高精度设备检测方法,提升5G海量通信效率。
Fast MLE and MAPE-Based Device Activity Detection for Grant-Free Access via PSCA and PSCA-Net
- 基于MLE与MAPE优化,设计并行迭代算法解决非凸问题。
- 相比现有方法,误码率降低且计算时间大幅缩短。
- 结合深度网络的PSCA-Net适合大规模低时延场景使用。
在5G及未来通信中,支持海量机器类通信(mMTC)和超可靠低时延通信(URLLC)的无许可接入面临设备活动检测速度与精度的双重挑战。现有方法存在误码率高或计算耗时长的问题。本文针对已知与未知路径损耗场景,提出基于最大似然估计(MLE)与最大后验估计(MAPE)的新检测方法,利用优化与深度学习技术实现更优的性能权衡。研究了四种非凸优化问题,首次构建其中一个MAPE模型。对每个问题,设计基于并行连续凸逼近(PSCA)的创新并行迭代算法,具备二次信息利用、低每轮复杂度、收敛至驻点等优势。进一步将各算法深度展开为名为PSCA-Net的神经网络,融合并行计算机制与可调步长优化,显著加速收敛。数值结果表明,所提方法在误码率与计算时间上均显著优于当前最优方法,展现出在无许可接入中的重要应用价值。
原文摘要 · Abstract (English)
Fast and accurate device activity detection is the critical challenge in grant-free access for supporting massive machine-type communications (mMTC) and ultra-reliable low-latency communications (URLLC) in 5G and beyond. The state-of-the-art methods have unsatisfactory error rates or computation times. To address these outstanding issues, we propose new maximum likelihood estimation (MLE) and maximum a posterior estimation (MAPE) based device activity detection methods for known and unknown pathloss that achieve superior error rate and computation time tradeoffs using optimization and deep learning techniques. Specifically, we investigate four non-convex optimization problems for MLE and MAPE in the two pathloss cases, with one MAPE problem being formulated for the first time. For each non-convex problem, we develop an innovative parallel iterative algorithm using the parallel successive convex approximation (PSCA) method. Each PSCA-based algorithm allows parallel computations, uses up to the objective function's second-order information, converges to the problem's stationary points, and has a low per-iteration computational complexity compared to the state-of-the-art algorithms. Then, for each PSCA-based iterative algorithm, we present a deep unrolling neural network implementation, called PSCA-Net, to further reduce the computation time. Each PSCA-Net elegantly marries the underlying PSCA-based algorithm's parallel computation mechanism with the parallelizable neural network architecture and effectively optimizes its step sizes based on vast data samples to speed up the convergence. Numerical results demonstrate that the proposed methods can significantly reduce the error rate and computation time compared to the state-of-the-art methods, revealing their significant values for grant-free access.
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