超大规模脉冲神经网络硬件软件协同设计，支持毫秒级实时推理。
HiAER-Spike: Hardware-Software Co-Design for Large-Scale Reconfigurable Event-Driven Neuromorphic Computing
- 采用分层地址事件路由架构，实现大规模脉冲信号高效传输。
- 可运行含1.6亿神经元、400亿突触的网络，速度超小鼠脑实时光速。
- 提供免配置的Python接口，适合科研与边缘/云端部署。
本文介绍HiAER-Spike，一种模块化、可重构、事件驱动的类脑计算平台，可执行最大达1.6亿神经元和400亿突触的脉冲神经网络，性能约为小鼠脑神经元数量的两倍，且运行速度超过真实时间。该系统正在加州大学圣地亚哥分校超级计算中心构建中，包含软硬件协同设计的完整栈，针对运行时大规模并行处理与分层地址事件路由（HiAER）进行优化，同时实现内存高效的网络存储与执行。架构能有效处理稀疏连接与稀疏活动，支持鲁棒、低延迟的事件驱动推理，适用于边缘与云场景。系统提供无硬件细节依赖的Python编程接口，用户可自由定义任意拓扑的脉冲神经网络，几乎无约束。通过网页门户向社区开放使用。本文概述软硬件栈设计、底层原理，展示系统能力，并邀请类脑计算领域同行反馈。
原文摘要 · Abstract (English)
In this work, we present HiAER-Spike, a modular, reconfigurable, event-driven neuromorphic computing platform designed to execute large spiking neural networks with up to 160 million neurons and 40 billion synapses - roughly twice the neurons of a mouse brain at faster-than real-time. This system, which is currently under construction at the UC San Diego Supercomputing Center, comprises a co-designed hard- and software stack that is optimized for run-time massively parallel processing and hierarchical address-event routing (HiAER) of spikes while promoting memory-efficient network storage and execution. Our architecture efficiently handles both sparse connectivity and sparse activity for robust and low-latency event-driven inference for both edge and cloud computing. A Python programming interface to HiAER-Spike, agnostic to hardware-level detail, shields the user from complexity in the configuration and execution of general spiking neural networks with virtually no constraints in topology. The system is made easily available over a web portal for use by the wider community. In the following we provide an overview of the hard- and software stack, explain the underlying design principles, demonstrate some of the system's capabilities and solicit feedback from the broader neuromorphic community.
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