用SRAM存算一体实现超低功耗快速求解最大割问题
A 10.8mW Mixed-Signal Simulated Bifurcation Ising Solver using SRAM Compute-In-Memory with 0.6us Time-to-Solution
- 采用SRAM存算一体架构加速模拟分岔算法
- 0.6微秒内达成93%以上最优解，功耗仅10.8毫瓦
- 适合需要高速低功耗优化的硬件部署场景
组合优化问题在金融、无线网络等领域具有基础意义。本文在CMOS工艺中实现了一种用于求解NP难优化问题的模拟分岔(Ising)求解器。由于模拟分岔算法需要固有噪声和注入噪声，模拟域计算展现出优势。本工作创新性地使用SRAM存算一体结构加速分岔过程，并在模拟域生成与注入最优衰减噪声。提出一种新型10-T SRAM单元，支持三值乘法运算。在TSMC 180nm CMOS工艺下，针对60节点、50%密度的随机二值最大割图（MAXCUT），该全连接求解器可在0.6微秒内可靠获得高于93%基态解，平均功耗为10.8毫瓦。相比此前提出的各类CMOS及其他平台上的Ising求解器，该芯片在时间-求解和功耗方面均提升一个数量级。
原文摘要 · Abstract (English)
Combinatorial optimization problems are funda- mental for various fields ranging from finance to wireless net- works. This work presents a simulated bifurcation (SB) Ising solver in CMOS for NP-hard optimization problems. Analog domain computing led to a superior implementation of this algorithm as inherent and injected noise is required in SB Ising solvers. The architecture novelties include the use of SRAM compute-in-memory (CIM) to accelerate bifurcation as well as the generation and injection of optimal decaying noise in the analog domain. We propose a novel 10-T SRAM cell capable of performing ternary multiplication. When measured with 60- node, 50% density, random, binary MAXCUT graphs, this all- to-all connected Ising solver reliably achieves above 93% of the ground state solution in 0.6us with 10.8mW average power in TSMC 180nm CMOS. Our chip achieves an order of magnitude improvement in time-to-solution and power compared to previously proposed Ising solvers in CMOS and other platforms.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。