用硬件感知算法提升模拟芯片的随机计算能力
A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning
- 基于自旋电路实现440个比特的芝诺图求解
- 0.44平方毫米面积内完成逻辑与优化任务
- 适合需要低功耗的AI与机器学习场景
本文展示了一款受概率比特物理启发的求解器芯片，配置了440个自旋比特，以芝诺图结构布局，占据0.44平方毫米面积。通过电流模式神经元更新电路、模拟模块与数字模块对齐的标准单元设计，以及模拟与数字共用电源，实现了高面积效率。训练过程中采用硬件感知对比散度算法，有效缓解工艺变异带来的失配问题。芯片验证了其在建模逻辑门、全加器及最大割（MaxCut）优化等任务上的可行性，展现了在人工智能与机器学习中的应用潜力。
原文摘要 · Abstract (English)
This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update circuit, standard cell design for analog blocks pitch-matched to digital blocks, and a shared power supply for both digital and analog components. Process variation related mismatches introduced by this approach are effectively mitigated using a hardware aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks such as modeling logic gates and full adders, as well as optimization tasks such as MaxCut, demonstrating its potential for AI and machine learning applications.
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