针对可重构硬件优化神经网络计算量，显著减少推理时的加法次数。
Coding for Computation: Efficient Compression of Neural Networks for Reconfigurable Hardware
- 通过正则化训练剪枝、权重共享与线性计算编码联合压缩模型。
- 在ResNet-34等大型网络上保持竞争力性能，同时大幅降低加法操作数。
- 适合部署于FPGA等资源受限的可重构硬件场景。
随着先进神经网络持续增大，其高效资源利用实现愈发重要。本文提出一种压缩方案，旨在降低在可重构硬件（如FPGA）上进行神经网络推理所需的计算量。该方法结合正则化训练剪枝、权重共享与线性计算编码（LCC），不同于传统以减少权重存储内存为目标的压缩技术，本方案专注于以硬件友好方式减少推理过程中的加法运算次数。实验表明，该方法在简单多层感知机及大规模深度网络（如ResNet-34）上均能保持良好性能，实现高效计算压缩。
原文摘要 · Abstract (English)
As state of the art neural networks (NNs) continue to grow in size, their resource-efficient implementation becomes ever more important. In this paper, we introduce a compression scheme that reduces the number of computations required for NN inference on reconfigurable hardware such as FPGAs. This is achieved by combining pruning via regularized training, weight sharing and linear computation coding (LCC). Contrary to common NN compression techniques, where the objective is to reduce the memory used for storing the weights of the NNs, our approach is optimized to reduce the number of additions required for inference in a hardware-friendly manner. The proposed scheme achieves competitive performance for simple multilayer perceptrons, as well as for large scale deep NNs such as ResNet-34.
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