用对比嵌入和引导修复，让大模型自动修Verilog代码漏洞。
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
- 通过对比嵌入提取代码内部信息，精准定位问题。
- 修复准确率达64.7%，远超开源模型（11.3）和GPT-3.5-turbo（36.6）。
- 统一检测与修复，适合硬件设计者快速调试Verilog代码。
大型语言模型在多种编程语言的调试中展现出巨大潜力，但其在Verilog调试中的应用仍不充分。本文提出VeriDebug，一种融合对比表示与引导修正能力的自动化Verilog调试方法。与现有方法不同，VeriDebug采用基于嵌入的技术精确检索内部信息，并进行缺陷修复。该方法通过共享参数空间统一实现Verilog错误检测与修正，同时学习错误模式与修复方案，借助对比嵌入与引导修正机制优化调试流程。实证结果表明，VeriDebugLoc-Type模型在修复任务上达到64.7%的准确率（Acc1），显著优于现有开源最优模型（11.3%）及更大的闭源模型GPT-3.5-turbo（36.6%），为传统调试方法提供了更优替代方案。
原文摘要 · Abstract (English)
Large Language Models (LLMs) have demonstrated remarkable potential in debugging for various programming languages. However, the application of LLMs to Verilog debugging remains insufficiently explored. Here, we present VeriDebug, an approach that integrates contrastive representation and guided correction capabilities for automated Verilog debugging. Unlike existing methods, VeriDebug employs an embedding-based technique to accurately retrieve internal information, followed by bug-fixing. VeriDebug unifies Verilog bug detection and correction through a shared parameter space. By simultaneously learning bug patterns and fixes, it streamlines debugging via contrastive embedding and guided correction. Empirical results show the efficacy of VeriDebug in enhancing Verilog debugging. Our VeriDebugLoc, Type model achieves 64.7 accuracy in bug fixing (Acc1), a significant improvement from the existing open-source SOTAs 11.3. This performance not only outperforms open-source alternatives but also exceeds larger closed-source models like GPT-3.5-turbo (36.6), offering a more accurate alternative to conventional debugging methods.
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