提出软硬件协同的细粒度低比特混合量化方法,提升大模型压缩效率与精度。
FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs
- 将权重分细粒度聚类并保护异常值,平衡精度与内存开销。
- 在接近当前最优平均位宽下实现更高模型精度,优于主流方法。
- 适配专用加速器,能效提升1.79倍,面积减少61.2%。
大语言模型(LLMs)显著推动自然语言处理发展,但对内存和计算资源要求极高。量化是降低模型内存消耗的有效手段,但现有高精度量化方法在极低比特下会出现严重精度下降。现有混合精度量化以粗粒度分组为单位,高精度分组导致内存开销大,低精度则损害模型性能。为此,我们提出 FineQ——面向低比特细粒度混合精度量化的软硬件协同设计。首先,将权重划分为更细粒度的聚类,并考虑聚类内异常值分布,实现精度与内存开销的平衡;其次,提出聚类内异常值保护机制,用3比特表示异常值,并设计索引与数据拼接编码方案,支持对齐内存访问;最后,引入采用时间编码的加速器,有效支持量化算法的同时简化卷积阵列中的乘法器。FineQ 在接近当前最优平均位宽下实现了更高的模型精度;同时,加速器达到最高1.79倍能效提升,并使卷积阵列面积减少61.2%。
原文摘要 · Abstract (English)
Large language models (LLMs) have significantly advanced the natural language processing paradigm but impose substantial demands on memory and computational resources. Quantization is one of the most effective ways to reduce memory consumption of LLMs. However, advanced single-precision quantization methods experience significant accuracy degradation when quantizing to ultra-low bits. Existing mixed-precision quantization methods are quantized by groups with coarse granularity. Employing high precision for group data leads to substantial memory overhead, whereas low precision severely impacts model accuracy. To address this issue, we propose FineQ, software-hardware co-design for low-bit fine-grained mixed-precision quantization of LLMs. First, FineQ partitions the weights into finer-grained clusters and considers the distribution of outliers within these clusters, thus achieving a balance between model accuracy and memory overhead. Then, we propose an outlier protection mechanism within clusters that uses 3 bits to represent outliers and introduce an encoding scheme for index and data concatenation to enable aligned memory access. Finally, we introduce an accelerator utilizing temporal coding that effectively supports the quantization algorithm while simplifying the multipliers in the systolic array. FineQ achieves higher model accuracy compared to the SOTA mixed-precision quantization algorithm at a close average bit-width. Meanwhile, the accelerator achieves up to 1.79x energy efficiency and reduces the area of the systolic array by 61.2%.
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