用大模型自动生成和优化硬件验证测试平台，大幅减少人工工作量。
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
- 基于大模型自动生成UVM测试平台并利用覆盖率反馈迭代优化
- 测试平台搭建时间缩短，代码与功能覆盖率分别达87.44%和89.58%
- 适合芯片验证工程师快速构建高质量测试用例
验证是集成电路开发中的主要瓶颈，占总开发工作量的近70%。尽管业界广泛采用通用验证方法学（UVM）通过结构化、可复用的测试平台提升效率，但构建测试平台和生成足够激励仍面临挑战，源于大量手动编码、重复执行EDA工具及对复杂设计的深入领域知识需求。本文提出UVM^2，一个基于大语言模型（LLM）的自动化验证框架，可生成UVM测试平台并依据覆盖率反馈迭代优化，显著降低人工投入同时保持严格验证标准。为评估UVM^2，我们构建了一个包含最多1.6K行代码的RTL设计基准套件。结果表明，相较于经验工程师，UVM^2将测试平台搭建时间大幅缩短，平均代码覆盖率和功能覆盖率分别达到87.44%和89.58%，优于现有最优方案20.96%和23.51%。
原文摘要 · Abstract (English)
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology (UVM) is widely used in industry to improve verification efficiency through structured and reusable testbenches, constructing these testbenches and generating sufficient stimuli remain challenging. These challenges arise from the considerable manual coding effort required, repetitive manual execution of multiple EDA tools, and the need for in-depth domain expertise to navigate complex designs.Here, we present UVM^2, an automated verification framework that leverages Large Language Models (LLMs) to generate UVM testbenches and iteratively refine them using coverage feedback, significantly reducing manual effort while maintaining rigorous verification standards.To evaluate UVM^2, we introduce a benchmark suite comprising Register Transfer Level (RTL) designs of up to 1.6K lines of code.The results show that UVM^2 reduces testbench setup time by up to UVM^2 compared to experienced engineers, and achieve average code and function coverage of 87.44% and 89.58%, outperforming state-of-the-art solutions by 20.96% and 23.51%, respectively.
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